/**
  ******************************************************************************
             Copyright(c) 2023 China Core Co. Ltd.
                      All Rights Reserved
  ******************************************************************************
  * @file    ioctrl_drv.h
  * @author  Product application department
  * @version V1.0
  * @date    2023.10.26
  * @brief   Header file of IO Control module.
  *
  ******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IOCTRL_DRV_H
#define __IOCTRL_DRV_H

#ifdef __cplusplus
extern "C"
{
#endif

/* Includes ------------------------------------------------------------------*/
#include "drv.h"
#include "type.h"
#include "status.h"

#ifdef FILE_OUT
/**@defgroup DRV 3 HAL driver
  *
  *@{
  */

/** @defgroup DRV_IOCTRL IOCTRL
  *
  *@{
  */
#endif
/*****************************Macros definition**********************************/
#ifdef FILE_OUT
/** @defgroup DRV_IOCTRL_Exported_Macros Exported Macros
  *
  * @{
  */
#endif

/* SPI pins define */
#define MISO_BIT_DEFINE (1 << 0)
#define MOSI_BIT_DEFINE (1 << 1)
#define SCK_BIT_DEFINE (1 << 2)
#define SS_BIT_DEFINE (1 << 3)

/* SPIM pins define */
#define SPIM_SS_BIT_DEFINE (1 << 0)
#define SPIM_SCK_BIT_DEFINE (1 << 1)
#define SPIM_D0_BIT_DEFINE (1 << 2)
#define SPIM_D1_BIT_DEFINE (1 << 3)
#define SPIM_D2_BIT_DEFINE (1 << 4)
#define SPIM_D3_BIT_DEFINE (1 << 5)

/* SPICR  */
#define _ioctrl_spi_pull_down(value)    _bit_clr(IOCTRL->SPICR, value)
#define _ioctrl_spi_pull_up(value)      _bit_set(IOCTRL->SPICR, value)
#define _ioctrl_spi1_ss_pull_down       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS1_PS)
#define _ioctrl_spi1_ss_pull_up         _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS1_PS)
#define _ioctrl_spi1_sck_pull_down      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK1_PS)
#define _ioctrl_spi1_sck_pull_up        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK1_PS)
#define _ioctrl_spi1_miso_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO1_PS)
#define _ioctrl_spi1_miso_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO1_PS)
#define _ioctrl_spi1_mosi_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI1_PS)
#define _ioctrl_spi1_mosi_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI1_PS)
#define _ioctrl_spi1_ss_input_dis       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS1_IE)
#define _ioctrl_spi1_ss_input_en        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS1_IE)
#define _ioctrl_spi1_sck_input_dis      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK1_IE)
#define _ioctrl_spi1_sck_input_en       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK1_IE)
#define _ioctrl_spi1_miso_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO1_IE)
#define _ioctrl_spi1_miso_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO1_IE)
#define _ioctrl_spi1_mosi_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI1_IE)
#define _ioctrl_spi1_mosi_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI1_IE)
#define _ioctrl_spi2_ss_pull_down       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS2_PS)
#define _ioctrl_spi2_ss_pull_up         _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS2_PS)
#define _ioctrl_spi2_sck_pull_down      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK2_PS)
#define _ioctrl_spi2_sck_pull_up        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK2_PS)
#define _ioctrl_spi2_miso_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO2_PS)
#define _ioctrl_spi2_miso_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO2_PS)
#define _ioctrl_spi2_mosi_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI2_PS)
#define _ioctrl_spi2_mosi_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI2_PS)
#define _ioctrl_spi2_ss_input_dis       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS2_IE)
#define _ioctrl_spi2_ss_input_en        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS2_IE)
#define _ioctrl_spi2_sck_input_dis      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK2_IE)
#define _ioctrl_spi2_sck_input_en       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK2_IE)
#define _ioctrl_spi2_miso_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO2_IE)
#define _ioctrl_spi2_miso_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO2_IE)
#define _ioctrl_spi2_mosi_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI2_IE)
#define _ioctrl_spi2_mosi_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI2_IE)
#define _ioctrl_spi3_ss_pull_down       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS3_PS)
#define _ioctrl_spi3_ss_pull_up         _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS3_PS)
#define _ioctrl_spi3_sck_pull_down      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK3_PS)
#define _ioctrl_spi3_sck_pull_up        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK3_PS)
#define _ioctrl_spi3_miso_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO3_PS)
#define _ioctrl_spi3_miso_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO3_PS)
#define _ioctrl_spi3_mosi_pull_down     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI3_PS)
#define _ioctrl_spi3_mosi_pull_up       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI3_PS)
#define _ioctrl_spi3_ss_input_dis       _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SS3_IE)
#define _ioctrl_spi3_ss_input_en        _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SS3_IE)
#define _ioctrl_spi3_sck_input_dis      _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_SCK3_IE)
#define _ioctrl_spi3_sck_input_en       _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_SCK3_IE)
#define _ioctrl_spi3_miso_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MISO3_IE)
#define _ioctrl_spi3_miso_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MISO3_IE)
#define _ioctrl_spi3_mosi_input_dis     _bit_clr(IOCTRL->SPICR, IOCTRL_SPICR_MOSI3_IE)
#define _ioctrl_spi3_mosi_input_en      _bit_set(IOCTRL->SPICR, IOCTRL_SPICR_MOSI3_IE)
#define _ioctrl_spi1_input_dis(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI1_IE))
#define _ioctrl_spi1_input_en(bits)     _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI1_IE))
#define _ioctrl_spi1_pull_down(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI1_PS))
#define _ioctrl_spi1_pull_up(bits)      _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI1_PS))
#define _ioctrl_spi2_input_dis(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI2_IE))
#define _ioctrl_spi2_input_en(bits)     _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI2_IE))
#define _ioctrl_spi2_pull_down(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI2_PS))
#define _ioctrl_spi2_pull_up(bits)      _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI2_PS))
#define _ioctrl_spi3_input_dis(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI3_IE))
#define _ioctrl_spi3_input_en(bits)     _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI3_IE))
#define _ioctrl_spi3_pull_down(bits)    _bit_clr(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI3_PS))
#define _ioctrl_spi3_pull_up(bits)      _bit_set(IOCTRL->SPICR, (bits << IOCTRL_SPICR_SPI3_PS))

/* I2CCR  */
#define _ioctrl_i2c_ds_2ma              _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_DS1_DS0)
#define _ioctrl_i2c_ds_4ma              _reg_modify(IOCTRL->I2CCR, ~IOCTRL_I2CCR_DS1_DS0, IOCTRL_I2CCR_DS1)
#define _ioctrl_i2c_ds_8ma              _reg_modify(IOCTRL->I2CCR, ~IOCTRL_I2CCR_DS1_DS0, IOCTRL_I2CCR_DS0)
#define _ioctrl_i2c_ds_12ma             _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_DS1_DS0)
#define _ioctrl_i2c_slew_fast           _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_SR)
#define _ioctrl_i2c_slew_slow           _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_SR)
#define _ioctrl_i2c_input_cmos          _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_IS)
#define _ioctrl_i2c_input_schmitt       _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_IS)
#define _ioctrl_i2c1_scl_pull_down      _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_SCL1_PS)
#define _ioctrl_i2c1_scl_pull_up        _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_SCL1_PS)
#define _ioctrl_i2c1_sda_pull_down      _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_SDA1_PS)
#define _ioctrl_i2c1_sda_pull_up        _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_SDA1_PS)
#define _ioctrl_i2c1_scl_input_dis      _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_SCL1_IE)
#define _ioctrl_i2c1_scl_input_en       _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_SCL1_IE)
#define _ioctrl_i2c1_sda_input_dis      _bit_clr(IOCTRL->I2CCR, IOCTRL_I2CCR_SDA1_IE)
#define _ioctrl_i2c1_sda_input_en       _bit_set(IOCTRL->I2CCR, IOCTRL_I2CCR_SDA1_IE)
#define _ioctrl_i2c1_input_dis(bits)    _bit_clr(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C1_IE))
#define _ioctrl_i2c1_input_en(bits)     _bit_set(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C1_IE))
#define _ioctrl_i2c1_pull_down(bits)    _bit_clr(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C1_PS))
#define _ioctrl_i2c1_pull_up(bits)      _bit_set(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C1_PS))
#define _ioctrl_i2c2_input_dis(bits)    _bit_clr(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C2_IE))
#define _ioctrl_i2c2_input_en(bits)     _bit_set(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C2_IE))
#define _ioctrl_i2c2_pull_down(bits)    _bit_clr(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C2_PS))
#define _ioctrl_i2c2_pull_up(bits)      _bit_set(IOCTRL->I2CCR, (bits << IOCTRL_I2CCR_I2C2_PS))


/* UARTCR  */
#define _ioctrl_uart_ds_2ma             _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_DS1_DS0)
#define _ioctrl_uart_ds_4ma             _reg_modify(IOCTRL->UARTCR, ~IOCTRL_UARTCR_DS1_DS0, IOCTRL_UARTCR_DS1)
#define _ioctrl_uart_ds_8ma             _reg_modify(IOCTRL->UARTCR, ~IOCTRL_UARTCR_DS1_DS0, IOCTRL_UARTCR_DS0)
#define _ioctrl_uart_ds_12ma            _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_DS1_DS0)
#define _ioctrl_uart_slew_fast          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_SR)
#define _ioctrl_uart_slew_slow          _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_SR)
#define _ioctrl_uart_input_cmos         _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_IS)
#define _ioctrl_uart_input_schmitt      _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_IS)
#define _ioctrl_uart1_txd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD1_PS)
#define _ioctrl_uart1_txd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD1_PS)
#define _ioctrl_uart1_rxd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD1_PS)
#define _ioctrl_uart1_rxd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD1_PS)
#define _ioctrl_uart1_cts_pull_down_dis _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS1_PUE)
#define _ioctrl_uart1_cts_pull_down_en  _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS1_PUE)
#define _ioctrl_uart2_txd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD2_PS)
#define _ioctrl_uart2_txd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD2_PS)
#define _ioctrl_uart2_rxd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD2_PS)
#define _ioctrl_uart2_rxd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD2_PS)
#define _ioctrl_uart2_cts_pull_down_dis _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS2_PUE)
#define _ioctrl_uart2_cts_pull_down_en  _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS2_PUE)
#define _ioctrl_uart3_txd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD3_PS)
#define _ioctrl_uart3_txd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_TXD3_PS)
#define _ioctrl_uart3_rxd_pull_down     _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD3_PS)
#define _ioctrl_uart3_rxd_pull_up       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_RXD3_PS)
#define _ioctrl_uart3_cts_pull_down_dis _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS3_PUE)
#define _ioctrl_uart3_cts_pull_down_en  _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_CTS3_PUE)
#define _ioctrl_uart_swap_load_dis      _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_LOAD_EN)
#define _ioctrl_uart_swap_load_en       _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_LOAD_EN)
#define _ioctrl_uart_swap_gint0         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT0)
#define _ioctrl_uart_swap_gint1         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT1)
#define _ioctrl_uart_swap_gint2         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT2)
#define _ioctrl_uart_swap_gint3         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT3)
#define _ioctrl_uart_swap_gint4         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT4)
#define _ioctrl_uart_swap_gint5         _bit_set(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT5)
#define _ioctrl_uart_swap_rxd1          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT0)
#define _ioctrl_uart_swap_txd1          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT4)
#define _ioctrl_uart_swap_rxd2          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT3)
#define _ioctrl_uart_swap_txd2          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT5)
#define _ioctrl_uart_swap_rxd3          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT2)
#define _ioctrl_uart_swap_txd3          _bit_clr(IOCTRL->UARTCR, IOCTRL_UARTCR_GINT_SWAP_BIT1)
#define _ioctrl_uart_swap_dis(bits)     _bit_clr(IOCTRL->UARTCR, bits << IOCTRL_UARTCR_GINT_SWAP)
#define _ioctrl_uart_swap_en(bits)      _bit_set(IOCTRL->UARTCR, bits << IOCTRL_UARTCR_GINT_SWAP)
#define _ioctrl_uart1_pull_down(bits)   _bit_clr(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART1_PS))
#define _ioctrl_uart1_pull_up(bits)     _bit_set(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART1_PS))
#define _ioctrl_uart2_pull_down(bits)   _bit_clr(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART2_PS))
#define _ioctrl_uart2_pull_up(bits)     _bit_set(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART2_PS))
#define _ioctrl_uart3_pull_down(bits)   _bit_clr(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART3_PS))
#define _ioctrl_uart3_pull_up(bits)     _bit_set(IOCTRL->UARTCR, (bits << IOCTRL_UARTCR_UART3_PS))

/* GINTLCR  */
#define _ioctrl_gintl_ds_2ma            _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_DS1_DS0)
#define _ioctrl_gintl_ds_4ma            _reg_modify(IOCTRL->GINTLCR, ~IOCTRL_GINTLCR_DS1_DS0, IOCTRL_GINTLCR_DS1)
#define _ioctrl_gintl_ds_8ma            _reg_modify(IOCTRL->GINTLCR, ~IOCTRL_GINTLCR_DS1_DS0, IOCTRL_GINTLCR_DS0)
#define _ioctrl_gintl_ds_12ma           _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_DS1_DS0)
#define _ioctrl_gintl_slew_fast         _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_SR)
#define _ioctrl_gintl_slew_slow         _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_SR)
#define _ioctrl_gintl_input_cmos        _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_IS)
#define _ioctrl_gintl_input_schmitt     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_IS)
#define _ioctrl_gintl_gint0_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT0_IE)
#define _ioctrl_gintl_gint0_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT0_IE)
#define _ioctrl_gintl_gint1_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT1_IE)
#define _ioctrl_gintl_gint1_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT1_IE)
#define _ioctrl_gintl_gint2_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT2_IE)
#define _ioctrl_gintl_gint2_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT2_IE)
#define _ioctrl_gintl_gint3_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT3_IE)
#define _ioctrl_gintl_gint3_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT3_IE)
#define _ioctrl_gintl_gint4_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT4_IE)
#define _ioctrl_gintl_gint4_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT4_IE)
#define _ioctrl_gintl_gint5_input_dis   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT5_IE)
#define _ioctrl_gintl_gint5_input_en    _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT5_IE)
#define _ioctrl_gintl_gint0_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT0_PS)
#define _ioctrl_gintl_gint0_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT0_PS)
#define _ioctrl_gintl_gint1_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT1_PS)
#define _ioctrl_gintl_gint1_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT1_PS)
#define _ioctrl_gintl_gint2_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT2_PS)
#define _ioctrl_gintl_gint2_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT2_PS)
#define _ioctrl_gintl_gint3_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT3_PS)
#define _ioctrl_gintl_gint3_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT3_PS)
#define _ioctrl_gintl_gint4_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT4_PS)
#define _ioctrl_gintl_gint4_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT4_PS)
#define _ioctrl_gintl_gint5_pull_down   _bit_clr(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT5_PS)
#define _ioctrl_gintl_gint5_pull_up     _bit_set(IOCTRL->GINTLCR, IOCTRL_GINTLCR_GINT5_PS)
#define _ioctrl_gintl_gints_input_dis(bits) _bit_clr(IOCTRL->GINTLCR, (bits << IOCTRL_GINTLCR_IE))
#define _ioctrl_gintl_gints_input_en(bits)  _bit_set(IOCTRL->GINTLCR, (bits << IOCTRL_GINTLCR_IE))
#define _ioctrl_gintl_gints_pull_down(bits) _bit_clr(IOCTRL->GINTLCR, (bits << IOCTRL_GINTLCR_PS))
#define _ioctrl_gintl_gints_pull_up(bits)   _bit_set(IOCTRL->GINTLCR, (bits << IOCTRL_GINTLCR_PS))

/* GINTHCR  */
#define _ioctrl_ginth_ds_2ma            _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_DS1_DS0)
#define _ioctrl_ginth_ds_4ma            _reg_modify(IOCTRL->GINTHCR, ~IOCTRL_GINTHCR_DS1_DS0, IOCTRL_GINTHCR_DS1)
#define _ioctrl_ginth_ds_8ma            _reg_modify(IOCTRL->GINTHCR, ~IOCTRL_GINTHCR_DS1_DS0, IOCTRL_GINTHCR_DS0)
#define _ioctrl_ginth_ds_12ma           _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_DS1_DS0)
#define _ioctrl_ginth_slew_fast         _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_SR)
#define _ioctrl_ginth_slew_slow         _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_SR)
#define _ioctrl_ginth_input_cmos        _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_IS)
#define _ioctrl_ginth_input_schmitt     _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_IS)
#define _ioctrl_ginth_gint12_input_dis  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT12_IE)
#define _ioctrl_ginth_gint12_input_en   _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT12_IE)
#define _ioctrl_ginth_gint13_input_dis  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT13_IE)
#define _ioctrl_ginth_gint13_input_en   _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT13_IE)
#define _ioctrl_ginth_gint14_input_dis  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT14_IE)
#define _ioctrl_ginth_gint14_input_en   _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT14_IE)
#define _ioctrl_ginth_gint15_input_dis  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT15_IE)
#define _ioctrl_ginth_gint15_input_en   _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT15_IE)
#define _ioctrl_ginth_gint13_pull_down  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT13_PS)
#define _ioctrl_ginth_gint13_pull_up    _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT13_PS)
#define _ioctrl_ginth_gint14_pull_down  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT14_PS)
#define _ioctrl_ginth_gint14_pull_up    _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT14_PS)
#define _ioctrl_ginth_gint15_pull_down  _bit_clr(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT15_PS)
#define _ioctrl_ginth_gint15_pull_up    _bit_set(IOCTRL->GINTHCR, IOCTRL_GINTHCR_GINT15_PS)
#define _ioctrl_ginth_gints_input_dis(bits) _bit_clr(IOCTRL->GINTHCR, (bits << IOCTRL_GINTHCR_IE))
#define _ioctrl_ginth_gints_input_en(bits)  _bit_set(IOCTRL->GINTHCR, (bits << IOCTRL_GINTHCR_IE))
#define _ioctrl_ginth_gints_pull_down(bits) _bit_clr(IOCTRL->GINTHCR, (bits << IOCTRL_GINTHCR_PS))
#define _ioctrl_ginth_gints_pull_up(bits)   _bit_set(IOCTRL->GINTHCR, (bits << IOCTRL_GINTHCR_PS))

/* SWAPCR */
#define _ioctrl_swapcr_swap0_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT0)   /**< 0:{ss3,sck3,miso3,mosi3}enable; 1:gint[8:11]enable */
#define _ioctrl_swapcr_swap0_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT0)   
#define _ioctrl_swapcr_swap1_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT1)   /**< 0:gint[15:14] enable; 1:gint[15:14] disable*/
#define _ioctrl_swapcr_swap1_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT1)  
#define _ioctrl_swapcr_swap2_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT2)   /**< 0:{txd2,rxd2} enable; 1:{txd2,rxd2} disable */
#define _ioctrl_swapcr_swap2_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT2)  
#define _ioctrl_swapcr_swap16_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT16) /**< 0:{txd3,rxd3} enable; 1:{txd3,rxd3} disable  */
#define _ioctrl_swapcr_swap16_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT16)   
#define _ioctrl_swapcr_swap17_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT17) /**< 0:gint[13] enable; 1:trace function enable  */
#define _ioctrl_swapcr_swap17_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT17)   
#define _ioctrl_swapcr_swap18_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT18) /**< 0:gint[14] enable; 1:uart1_rts enable  */
#define _ioctrl_swapcr_swap18_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT18) 
#define _ioctrl_swapcr_swap19_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT19) /**< 0:gint[15] enable; 1:uart1_cts enable  */
#define _ioctrl_swapcr_swap19_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT19) 
#define _ioctrl_swapcr_swap20_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT20) /**< reserved */
#define _ioctrl_swapcr_swap20_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT20) 
#define _ioctrl_swapcr_swap21_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT21) /**< 0:gint[13] enable; 1:uart2_cts enable  */
#define _ioctrl_swapcr_swap21_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT21) 
#define _ioctrl_swapcr_swap22_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT22) /**< reserved */
#define _ioctrl_swapcr_swap22_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT22) 
#define _ioctrl_swapcr_swap23_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT23) /**< reserved */
#define _ioctrl_swapcr_swap23_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT23) 
#define _ioctrl_swapcr_swap24_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT24) /**< 0:gint13 enable; 1:pwm0 enable  */
#define _ioctrl_swapcr_swap24_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT24) 
#define _ioctrl_swapcr_swap25_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT25) /**< 0:gint14 enable; 1:pwm1 enable  */
#define _ioctrl_swapcr_swap25_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT25) 
#define _ioctrl_swapcr_swap26_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT26) /**< 0:scl enable; 1:pwm2 enable  */
#define _ioctrl_swapcr_swap26_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT26) 
#define _ioctrl_swapcr_swap27_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT27) /**< 0:sda enable; 1:pwm3 enable  */
#define _ioctrl_swapcr_swap27_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT27) 
#define _ioctrl_swapcr_swap28_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT28) /**< 0:txd enable; 1:pwm4 enable  */
#define _ioctrl_swapcr_swap28_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT28) 
#define _ioctrl_swapcr_swap29_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT29) /**< 0:rxd enable; 1:pwm5 enable  */
#define _ioctrl_swapcr_swap29_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT29) 
#define _ioctrl_swapcr_swap30_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT30) /**< 0:txd2 enable; 1:pwm6 enable  */
#define _ioctrl_swapcr_swap30_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT30) 
#define _ioctrl_swapcr_swap31_clr _bit_clr(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT31) /**< 0:rxd2 enable; 1:pwm7 enable  */
#define _ioctrl_swapcr_swap31_set _bit_set(IOCTRL->SWAPCR, IOCTRL_SWAPCR_SWAP_BIT31) 

/* SPIM1CR  */
#define _ioctrl_spim1_d_ds_2ma          _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_DS1_DS0)
#define _ioctrl_spim1_d_ds_4ma          _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_D_DS1_DS0, IOCTRL_SPIM1CR_D_DS1)
#define _ioctrl_spim1_d_ds_8ma          _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_D_DS1_DS0, IOCTRL_SPIM1CR_D_DS0)
#define _ioctrl_spim1_d_ds_12ma         _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_DS1_DS0)
#define _ioctrl_spim1_d_slew_fast       _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_SR)
#define _ioctrl_spim1_d_slew_slow       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_SR)
#define _ioctrl_spim1_d_input_cmos      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_IS)
#define _ioctrl_spim1_d_input_schmitt   _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D_IS)

#define _ioctrl_spim1_pull_up_down_dis  _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_PUE)
#define _ioctrl_spim1_pull_up_down_en   _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_PUE)
#define _ioctrl_spim1_output_cmos       _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_ODE)
#define _ioctrl_spim1_output_open_d     _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_ODE)

#define _ioctrl_spim1_sck_ds_2ma        _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_DS1_DS0)
#define _ioctrl_spim1_sck_ds_4ma        _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_SCK_DS1_DS0, IOCTRL_SPIM1CR_SCK_DS1)
#define _ioctrl_spim1_sck_ds_8ma        _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_SCK_DS1_DS0, IOCTRL_SPIM1CR_SCK_DS0)
#define _ioctrl_spim1_sck_ds_12ma       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_DS1_DS0)
#define _ioctrl_spim1_sck_slew_fast     _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_SR)
#define _ioctrl_spim1_sck_slew_slow     _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_SR)
#define _ioctrl_spim1_sck_input_cmos    _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_IS)
#define _ioctrl_spim1_sck_input_schmitt _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_IS)

#define _ioctrl_spim1_ss_ds_2ma         _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_DS1_DS0)
#define _ioctrl_spim1_ss_ds_4ma         _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_SS_DS1_DS0, IOCTRL_SPIM1CR_SS_DS1)
#define _ioctrl_spim1_ss_ds_8ma         _reg_modify(IOCTRL->SPIM1CR, ~IOCTRL_SPIM1CR_SS_DS1_DS0, IOCTRL_SPIM1CR_SS_DS0)
#define _ioctrl_spim1_ss_ds_12ma        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_DS1_DS0)
#define _ioctrl_spim1_ss_slew_fast      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_SR)
#define _ioctrl_spim1_ss_slew_slow      _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_SR)
#define _ioctrl_spim1_ss_input_cmos     _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_IS)
#define _ioctrl_spim1_ss_input_schmitt  _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_IS)

#define _ioctrl_spim1_ss_pull_down      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_PS)
#define _ioctrl_spim1_ss_pull_up        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_PS)
#define _ioctrl_spim1_sck_pull_down     _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_PS)
#define _ioctrl_spim1_sck_pull_up       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_PS)
#define _ioctrl_spim1_d0_pull_down      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D0_PS)
#define _ioctrl_spim1_d0_pull_up        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D0_PS)
#define _ioctrl_spim1_d1_pull_down      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D1_PS)
#define _ioctrl_spim1_d1_pull_up        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D1_PS)
#define _ioctrl_spim1_d2_pull_down      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D2_PS)
#define _ioctrl_spim1_d2_pull_up        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D2_PS)
#define _ioctrl_spim1_d3_pull_down      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D3_PS)
#define _ioctrl_spim1_d3_pull_up        _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D3_PS)
#define _ioctrl_spim1_ss_input_dis      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_IE)
#define _ioctrl_spim1_ss_input_en       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SS_IE)
#define _ioctrl_spim1_sck_input_dis     _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_IE)
#define _ioctrl_spim1_sck_input_en      _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_SCK_IE)
#define _ioctrl_spim1_d0_input_dis      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D0_IE)
#define _ioctrl_spim1_d0_input_en       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D0_IE)
#define _ioctrl_spim1_d1_input_dis      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D1_IE)
#define _ioctrl_spim1_d1_input_en       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D1_IE)
#define _ioctrl_spim1_d2_input_dis      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D2_IE)
#define _ioctrl_spim1_d2_input_en       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D2_IE)
#define _ioctrl_spim1_d3_input_dis      _bit_clr(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D3_IE)
#define _ioctrl_spim1_d3_input_en       _bit_set(IOCTRL->SPIM1CR, IOCTRL_SPIM1CR_D3_IE)
#define _ioctrl_spim1_input_dis(bits)   _bit_clr(IOCTRL->SPIM1CR, (bits << IOCTRL_SPIM1CR_IE))
#define _ioctrl_spim1_input_en(bits)    _bit_set(IOCTRL->SPIM1CR, (bits << IOCTRL_SPIM1CR_IE))
#define _ioctrl_spim1_pull_down(bits)   _bit_clr(IOCTRL->SPIM1CR, (bits << IOCTRL_SPIM1CR_PS))
#define _ioctrl_spim1_pull_up(bits)     _bit_set(IOCTRL->SPIM1CR, (bits << IOCTRL_SPIM1CR_PS))

/*WKUPPADCR*/
#define _ioctrl_wkuppadcr_ds_2ma        _bit_clr(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_DS1_DS0)
#define _ioctrl_wkuppadcr_ds_4ma        _reg_modify(IOCTRL->WKUPPADCR, ~IOCTRL_WKUPPADCR_DS1_DS0, IOCTRL_WKUPPADCR_DS1)
#define _ioctrl_wkuppadcr_ds_8ma        _reg_modify(IOCTRL->WKUPPADCR, ~IOCTRL_WKUPPADCR_DS1_DS0, IOCTRL_WKUPPADCR_DS0)
#define _ioctrl_wkuppadcr_ds_12ma       _bit_set(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_DS1_DS0)
#define _ioctrl_wkuppadcr_slew_fast     _bit_clr(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_SR)
#define _ioctrl_wkuppadcr_slew_slow     _bit_set(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_SR)
#define _ioctrl_wkuppadcr_input_cmos    _bit_clr(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_IS)
#define _ioctrl_wkuppadcr_input_schmitt _bit_set(IOCTRL->WKUPPADCR, IOCTRL_WKUPPADCR_IS)

/*EPORT2CR*/
#define _ioctrl_eport2cr_gints_input_dis(bits)  _bit_clr(IOCTRL->EPORT2CR, (bits << IOCTRL_EPORT2CR_IE))
#define _ioctrl_eport2cr_gints_input_en(bits)   _bit_set(IOCTRL->EPORT2CR, (bits << IOCTRL_EPORT2CR_IE))
#define _ioctrl_eport2cr_bit0_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT0)
#define _ioctrl_eport2cr_bit0_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT0)
#define _ioctrl_eport2cr_bit1_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT1)
#define _ioctrl_eport2cr_bit1_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT1)
#define _ioctrl_eport2cr_bit2_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT2)
#define _ioctrl_eport2cr_bit2_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT2)
#define _ioctrl_eport2cr_bit3_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT3)
#define _ioctrl_eport2cr_bit3_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT3)
#define _ioctrl_eport2cr_bit4_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT4)
#define _ioctrl_eport2cr_bit4_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT4)
#define _ioctrl_eport2cr_bit5_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT5)
#define _ioctrl_eport2cr_bit5_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT5)
#define _ioctrl_eport2cr_bit6_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT6)
#define _ioctrl_eport2cr_bit6_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT6)
#define _ioctrl_eport2cr_bit7_input_dis         _bit_clr(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT7)
#define _ioctrl_eport2cr_bit7_input_en          _bit_set(IOCTRL->EPORT2CR, IOCTRL_EPORT2CR_IE_BIT7)

/*EPORT5CR*/
#define _ioctrl_eport5cr_gints_input_dis(bits)  _bit_clr(IOCTRL->EPORT5CR, (bits << IOCTRL_EPORT5CR_IE))
#define _ioctrl_eport5cr_gints_input_en(bits)   _bit_set(IOCTRL->EPORT5CR, (bits << IOCTRL_EPORT5CR_IE))
#define _ioctrl_eport5cr_bit0_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT0)
#define _ioctrl_eport5cr_bit0_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT0)
#define _ioctrl_eport5cr_bit1_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT1)
#define _ioctrl_eport5cr_bit1_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT1)
#define _ioctrl_eport5cr_bit2_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT2)
#define _ioctrl_eport5cr_bit2_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT2)
#define _ioctrl_eport5cr_bit3_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT3)
#define _ioctrl_eport5cr_bit3_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT3)
#define _ioctrl_eport5cr_bit4_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT4)
#define _ioctrl_eport5cr_bit4_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT4)
#define _ioctrl_eport5cr_bit5_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT5)
#define _ioctrl_eport5cr_bit5_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT5)
#define _ioctrl_eport5cr_bit6_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT6)
#define _ioctrl_eport5cr_bit6_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT6)
#define _ioctrl_eport5cr_bit7_input_dis         _bit_clr(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT7)
#define _ioctrl_eport5cr_bit7_input_en          _bit_set(IOCTRL->EPORT5CR, IOCTRL_EPORT5CR_IE_BIT7)


/*EPORT6CR*/
#define _ioctrl_eport6cr_gints_input_dis(bits)  _bit_clr(IOCTRL->EPORT6CR, (bits << IOCTRL_EPORT6CR_IE))
#define _ioctrl_eport6cr_gints_input_en(bits)   _bit_set(IOCTRL->EPORT6CR, (bits << IOCTRL_EPORT6CR_IE))
#define _ioctrl_eport6cr_bit0_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT0)
#define _ioctrl_eport6cr_bit0_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT0)
#define _ioctrl_eport6cr_bit1_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT1)
#define _ioctrl_eport6cr_bit1_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT1)
#define _ioctrl_eport6cr_bit2_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT2)
#define _ioctrl_eport6cr_bit2_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT2)
#define _ioctrl_eport6cr_bit3_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT3)
#define _ioctrl_eport6cr_bit3_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT3)
#define _ioctrl_eport6cr_bit4_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT4)
#define _ioctrl_eport6cr_bit4_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT4)
#define _ioctrl_eport6cr_bit5_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT5)
#define _ioctrl_eport6cr_bit5_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT5)
#define _ioctrl_eport6cr_bit6_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT6)
#define _ioctrl_eport6cr_bit6_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT6)
#define _ioctrl_eport6cr_bit7_input_dis         _bit_clr(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT7)
#define _ioctrl_eport6cr_bit7_input_en          _bit_set(IOCTRL->EPORT6CR, IOCTRL_EPORT6CR_IE_BIT7)

/*EPORT7CR*/
#define _ioctrl_eport7cr_gints_input_dis(bits)  _bit_clr(IOCTRL->EPORT7CR, (bits << IOCTRL_EPORT7CR_IE))
#define _ioctrl_eport7cr_gints_input_en(bits)   _bit_set(IOCTRL->EPORT7CR, (bits << IOCTRL_EPORT7CR_IE))
#define _ioctrl_eport7cr_bit0_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT0)
#define _ioctrl_eport7cr_bit0_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT0)
#define _ioctrl_eport7cr_bit1_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT1)
#define _ioctrl_eport7cr_bit1_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT1)
#define _ioctrl_eport7cr_bit2_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT2)
#define _ioctrl_eport7cr_bit2_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT2)
#define _ioctrl_eport7cr_bit3_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT3)
#define _ioctrl_eport7cr_bit3_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT3)
#define _ioctrl_eport7cr_bit4_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT4)
#define _ioctrl_eport7cr_bit4_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT4)
#define _ioctrl_eport7cr_bit5_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT5)
#define _ioctrl_eport7cr_bit5_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT5)
#define _ioctrl_eport7cr_bit6_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT6)
#define _ioctrl_eport7cr_bit6_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT6)
#define _ioctrl_eport7cr_bit7_input_dis         _bit_clr(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT7)
#define _ioctrl_eport7cr_bit7_input_en          _bit_set(IOCTRL->EPORT7CR, IOCTRL_EPORT7CR_IE_BIT7)

/*SWAPCR2*/
#define _ioctrl_swapcr2_swap8_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT8) /**< 0:ss1 enable; 1:gint[40] enable  */
#define _ioctrl_swapcr2_swap8_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT8)
#define _ioctrl_swapcr2_swap9_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT9) /**< 0:sck1 enable; 1:gint[41] enable  */
#define _ioctrl_swapcr2_swap9_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT9)
#define _ioctrl_swapcr2_swap10_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT10) /**< 0:miso1 enable; 1:gint[42] disable  */
#define _ioctrl_swapcr2_swap10_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT10)
#define _ioctrl_swapcr2_swap11_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT11) /**< 0:mosi1 enable; 1:gint[43] enable  */
#define _ioctrl_swapcr2_swap11_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT11)
#define _ioctrl_swapcr2_swap12_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT12) /**< 0:ss2 enable; 1:gint[44] enable  */
#define _ioctrl_swapcr2_swap12_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT12)
#define _ioctrl_swapcr2_swap13_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT13) /**< 0:sck2 enable; 1:gint[45] enable  */
#define _ioctrl_swapcr2_swap13_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT13)
#define _ioctrl_swapcr2_swap14_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT14) /**< 0:miso2 enable; 1:gint[46] enable */
#define _ioctrl_swapcr2_swap14_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT14)
#define _ioctrl_swapcr2_swap15_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT15) /**< 0:mosi2 enable; 1:gint[47] enable */
#define _ioctrl_swapcr2_swap15_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT15)
#define _ioctrl_swapcr2_swap18_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT18) /**< 0:scl enable; 1:gint[50] enable  */
#define _ioctrl_swapcr2_swap18_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT18)
#define _ioctrl_swapcr2_swap19_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT19) /**< 0:sda enable; 1:gint[51] enable  */
#define _ioctrl_swapcr2_swap19_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT19)
#define _ioctrl_swapcr2_swap20_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT20) /**< 0:txd enable; 1:gint[52] enable  */
#define _ioctrl_swapcr2_swap20_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT20)
#define _ioctrl_swapcr2_swap21_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT21) /**< 0:rxd enable; 1:gint[53] enable  */
#define _ioctrl_swapcr2_swap21_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT21)
#define _ioctrl_swapcr2_swap22_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT22) /**< 0:txd2 enable; 1:gint[54] enable  */
#define _ioctrl_swapcr2_swap22_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT22)
#define _ioctrl_swapcr2_swap23_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT23) /**< 0:rxd2 enable; 1:gint[55] enable  */
#define _ioctrl_swapcr2_swap23_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT23)
#define _ioctrl_swapcr2_swap24_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT24) /**< 0:txd3 enable; 1:gint[56] enable  */
#define _ioctrl_swapcr2_swap24_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT24)
#define _ioctrl_swapcr2_swap25_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT25) /**< 0:rxd3 enable; 1:gint[57] enable  */
#define _ioctrl_swapcr2_swap25_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT25)
#define _ioctrl_swapcr2_swap26_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT26) /**< 0:isodat2 enable; 1:gint[58] enable  */
#define _ioctrl_swapcr2_swap26_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT26)
#define _ioctrl_swapcr2_swap27_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT27) /**< 0:isoclk2 enable; 1:gint[59] enable  */
#define _ioctrl_swapcr2_swap27_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT27)
#define _ioctrl_swapcr2_swap28_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT28) /**< 0:isorst2 enable; 1:gint[60] enable  */
#define _ioctrl_swapcr2_swap28_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT28)
#define _ioctrl_swapcr2_swap29_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT29) /**< 0:isodat1 enable; 1:gint[61] enable  */
#define _ioctrl_swapcr2_swap29_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT29)
#define _ioctrl_swapcr2_swap30_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT30) /**< 0:wakeup enable; 1:gint[62] enable  */
#define _ioctrl_swapcr2_swap30_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT30)
#define _ioctrl_swapcr2_swap31_clr _bit_clr(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT31) /**< 0:usbdet enable; 1:gint[63] enable  */
#define _ioctrl_swapcr2_swap31_set _bit_set(IOCTRL->SWAPCR2, IOCTRL_SWAPCR2_SWAP_BIT31)

/*SWAPCR3*/
#define _ioctrl_swapcr3_swap0_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT0) /**< 0:isoclk1 enable; 1:gint[6]enable */
#define _ioctrl_swapcr3_swap0_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT0)
#define _ioctrl_swapcr3_swap1_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT1) /**< 0:isorst1 enable; 1:gint[7] enable*/
#define _ioctrl_swapcr3_swap1_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT1)
#define _ioctrl_swapcr3_swap2_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT2) /**< 1:pwmt1_etr enable; 0:gint[14] enable */
#define _ioctrl_swapcr3_swap2_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT2)
#define _ioctrl_swapcr3_swap3_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT3) /**< 1:pwmt1_brk enable; 0:gint[15] enable */
#define _ioctrl_swapcr3_swap3_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT3)
#define _ioctrl_swapcr3_swap4_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT4) /**< 1:pwmt2_etr enable; 0:miso3 enable */
#define _ioctrl_swapcr3_swap4_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT4)
#define _ioctrl_swapcr3_swap5_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT5) /**< 1:pwmt2_brk enable; 0:mosi3 enable */
#define _ioctrl_swapcr3_swap5_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT5)
#define _ioctrl_swapcr3_swap6_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT6) /**< 1:pwmt3_etr enable; 0:ss3 enable */
#define _ioctrl_swapcr3_swap6_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT6)
#define _ioctrl_swapcr3_swap7_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT7) /**< 1:pwmt3_brk enable; 0:sck3 enable */
#define _ioctrl_swapcr3_swap7_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT7)
#define _ioctrl_swapcr3_swap8_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT8) /**< 1:pwmt1_ch0 enable; 0:gint[0] enable */
#define _ioctrl_swapcr3_swap8_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT8)
#define _ioctrl_swapcr3_swap9_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT9) /**< 1:pwmt1_ch0n enable; 0:gint[1] enable */
#define _ioctrl_swapcr3_swap9_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT9)
#define _ioctrl_swapcr3_swap10_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT10) /**< 1:pwmt1_ch1 enable; 0:isoclk1 enable */
#define _ioctrl_swapcr3_swap10_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT10)
#define _ioctrl_swapcr3_swap11_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT11) /**< 1:pwmt1_ch1n enable; 0:isorst1 enable */
#define _ioctrl_swapcr3_swap11_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT11)
#define _ioctrl_swapcr3_swap12_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT12) /**< 1:pwmt1_ch2 enable; 0:gint[2] enable */
#define _ioctrl_swapcr3_swap12_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT12)
#define _ioctrl_swapcr3_swap13_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT13) /**< 1:pwmt1_ch2n enable; 0:gint[4] enable */
#define _ioctrl_swapcr3_swap13_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT13)
#define _ioctrl_swapcr3_swap14_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT14) /**< 1:pwmt1_ch3 enable; 0:gint[3] enable */
#define _ioctrl_swapcr3_swap14_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT14)
#define _ioctrl_swapcr3_swap15_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT15) /**< 1:pwmt1_ch3n enable; 0:gint[5] enable */
#define _ioctrl_swapcr3_swap15_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT15)
#define _ioctrl_swapcr3_swap16_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT16) /**< 1:pwmt2_ch0 enable; 0:usbdet enable */
#define _ioctrl_swapcr3_swap16_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT16)
#define _ioctrl_swapcr3_swap17_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT17) /**< 1:pwmt2_ch0n enable; 0:isodat2 enable */
#define _ioctrl_swapcr3_swap17_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT17)
#define _ioctrl_swapcr3_swap18_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT18) /**< 1:pwmt2_ch1 enable; 0:wakeup enable */
#define _ioctrl_swapcr3_swap18_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT18)
#define _ioctrl_swapcr3_swap19_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT19) /**< 1:pwmt2_ch1n enable; 0:isoclk2 enable */
#define _ioctrl_swapcr3_swap19_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT19)
#define _ioctrl_swapcr3_swap20_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT20) /**< 1:pwmt2_ch2 enable; 0:clkout enable */
#define _ioctrl_swapcr3_swap20_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT20)
#define _ioctrl_swapcr3_swap21_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT21) /**< 1:pwmt2_ch2n enable; 0:isorst2 enable */
#define _ioctrl_swapcr3_swap21_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT21)
#define _ioctrl_swapcr3_swap22_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT22) /**< 1:pwmt2_ch3 enable; 0:rstout enable */
#define _ioctrl_swapcr3_swap22_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT22)
#define _ioctrl_swapcr3_swap23_clr _bit_clr(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT23) /**< 1:pwmt2_ch3n enable; 0:isodat1 enable */
#define _ioctrl_swapcr3_swap23_set _bit_set(IOCTRL->SWAPCR3, IOCTRL_SWAPCR3_SWAP_BIT23)

/*SWAPCR4*/
#define _ioctrl_swapcr4_swap20_clr _bit_clr(IOCTRL->SWAPCR4, IOCTRL_SWAPCR4_SWAP_BIT20) /**< 0:clkout enable; 1:gint[22] enable */
#define _ioctrl_swapcr4_swap20_set _bit_set(IOCTRL->SWAPCR4, IOCTRL_SWAPCR4_SWAP_BIT20)
#define _ioctrl_swapcr4_swap21_clr _bit_clr(IOCTRL->SWAPCR4, IOCTRL_SWAPCR4_SWAP_BIT21) /**< 0:rstout enable; 1:gint[23] enable */
#define _ioctrl_swapcr4_swap21_set _bit_set(IOCTRL->SWAPCR4, IOCTRL_SWAPCR4_SWAP_BIT21)

/*SWAPCR5*/
#define _ioctrl_swapcr5_swap_dis(bits) _bit_clr(IOCTRL->SWAPCR5, bits <<20)
#define _ioctrl_swapcr5_swap_en(bits) _bit_set(IOCTRL->SWAPCR5, bits << 20)
#define _ioctrl_swapcr5_swap4_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT4) /**< 1:gint[16] enable; 0:spi4[2] enable */
#define _ioctrl_swapcr5_swap4_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT4)
#define _ioctrl_swapcr5_swap5_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT5) /**< 1:gint[17] enable; 0:spi4[3] enable */
#define _ioctrl_swapcr5_swap5_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT5)
#define _ioctrl_swapcr5_swap6_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT6) /**< 1:gint[18] enable; 0:spi4[0] enable */
#define _ioctrl_swapcr5_swap6_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT6)
#define _ioctrl_swapcr5_swap7_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT7) /**< 1:gint[19] enable; 0:spi4[1] enable */
#define _ioctrl_swapcr5_swap7_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT7)
#define _ioctrl_swapcr5_swap8_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT8) /**< 1:gint[20] enable; 0:spi4_sck enable */
#define _ioctrl_swapcr5_swap8_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT8)
#define _ioctrl_swapcr5_swap9_clr _bit_clr(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT9) /**< 1:gint[21] enable; 0:spi4_ss enable */
#define _ioctrl_swapcr5_swap9_set _bit_set(IOCTRL->SWAPCR5, IOCTRL_SWAPCR5_SWAP_BIT9)

/*PWMTCR*/
#define _ioctrl_pwmtcr_pwmt1_etr_pull_up_down_dis   _bit_clr(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT1_ETR_PUE)
#define _ioctrl_pwmtcr_pwmt1_etr_pull_up_down_en    _bit_set(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT1_ETR_PUE)
#define _ioctrl_pwmtcr_pwmt1_brk_pull_up_down_dis   _bit_clr(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT1_BRK_PUE)
#define _ioctrl_pwmtcr_pwmt1_brk_pull_up_down_en    _bit_set(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT1_BRK_PUE)
#define _ioctrl_pwmtcr_pwmt2_etr_pull_up_down_dis   _bit_clr(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT2_ETR_PUE)
#define _ioctrl_pwmtcr_pwmt2_etr_pull_up_down_en    _bit_set(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT2_ETR_PUE)
#define _ioctrl_pwmtcr_pwmt2_brk_pull_up_down_dis   _bit_clr(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT2_BRK_PUE)
#define _ioctrl_pwmtcr_pwmt2_brk_pull_up_down_en    _bit_set(IOCTRL->PWMTCR, IOCTRL_PWMTCR_PWMT2_BRK_PUE)

/*SPI1CR*/
#define _ioctrl_spi1_d_ds_2ma                       _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_DS1_DS0)
#define _ioctrl_spi1_d_ds_4ma                       _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_D_DS1_DS0, IOCTRL_SPI1CR_D_DS1)
#define _ioctrl_spi1_d_ds_8ma                       _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_D_DS1_DS0, IOCTRL_SPI1CR_D_DS0)
#define _ioctrl_spi1_d_ds_12ma                      _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_DS1_DS0)
#define _ioctrl_spi1_d_slew_fast                    _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_SR)
#define _ioctrl_spi1_d_slew_slow                    _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_SR)
#define _ioctrl_spi1_d_input_cmos                   _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_IS)
#define _ioctrl_spi1_d_input_schmitt                _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_D_IS)

#define _ioctrl_spi1_sck_ds_2ma                     _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_DS1_DS0)
#define _ioctrl_spi1_sck_ds_4ma                     _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_SCK_DS1_DS0, IOCTRL_SPI1CR_SCK_DS1)
#define _ioctrl_spi1_sck_ds_8ma                     _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_SCK_DS1_DS0, IOCTRL_SPI1CR_SCK_DS0)
#define _ioctrl_spi1_sck_ds_12ma                    _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_DS1_DS0)
#define _ioctrl_spi1_sck_slew_fast                  _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_SR)
#define _ioctrl_spi1_sck_slew_slow                  _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_SR)
#define _ioctrl_spi1_sck_input_cmos                 _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_IS)
#define _ioctrl_spi1_sck_input_schmitt              _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SCK_IS)

#define _ioctrl_spi1_ss_ds_2ma                      _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_DS1_DS0)
#define _ioctrl_spi1_ss_ds_4ma                      _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_SS_DS1_DS0, IOCTRL_SPI1CR_SS_DS1)
#define _ioctrl_spi1_ss_ds_8ma                      _reg_modify(IOCTRL->SPI1CR, ~IOCTRL_SPI1CR_SS_DS1_DS0, IOCTRL_SPI1CR_SS_DS0)
#define _ioctrl_spi1_ss_ds_12ma                     _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_DS1_DS0)
#define _ioctrl_spi1_ss_slew_fast                   _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_SR)
#define _ioctrl_spi1_ss_slew_slow                   _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_SR)
#define _ioctrl_spi1_ss_input_cmos                  _bit_clr(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_IS)
#define _ioctrl_spi1_ss_input_schmitt               _bit_set(IOCTRL->SPI1CR, IOCTRL_SPI1CR_SS_IS)

/*SPI2CR*/
#define _ioctrl_spi2_d_ds_2ma                       _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_DS1_DS0)
#define _ioctrl_spi2_d_ds_4ma                       _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_D_DS1_DS0, IOCTRL_SPI2CR_D_DS1)
#define _ioctrl_spi2_d_ds_8ma                       _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_D_DS1_DS0, IOCTRL_SPI2CR_D_DS0)
#define _ioctrl_spi2_d_ds_12ma                      _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_DS1_DS0)
#define _ioctrl_spi2_d_slew_fast                    _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_SR)
#define _ioctrl_spi2_d_slew_slow                    _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_SR)
#define _ioctrl_spi2_d_input_cmos                   _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_IS)
#define _ioctrl_spi2_d_input_schmitt                _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_D_IS)

#define _ioctrl_spi2_sck_ds_2ma                     _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_DS1_DS0)
#define _ioctrl_spi2_sck_ds_4ma                     _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_SCK_DS1_DS0, IOCTRL_SPI2CR_SCK_DS1)
#define _ioctrl_spi2_sck_ds_8ma                     _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_SCK_DS1_DS0, IOCTRL_SPI2CR_SCK_DS0)
#define _ioctrl_spi2_sck_ds_12ma                    _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_DS1_DS0)
#define _ioctrl_spi2_sck_slew_fast                  _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_SR)
#define _ioctrl_spi2_sck_slew_slow                  _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_SR)
#define _ioctrl_spi2_sck_input_cmos                 _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_IS)
#define _ioctrl_spi2_sck_input_schmitt              _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SCK_IS)

#define _ioctrl_spi2_ss_ds_2ma                      _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_DS1_DS0)
#define _ioctrl_spi2_ss_ds_4ma                      _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_SS_DS1_DS0, IOCTRL_SPI2CR_SS_DS1)
#define _ioctrl_spi2_ss_ds_8ma                      _reg_modify(IOCTRL->SPI2CR, ~IOCTRL_SPI2CR_SS_DS1_DS0, IOCTRL_SPI2CR_SS_DS0)
#define _ioctrl_spi2_ss_ds_12ma                     _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_DS1_DS0)
#define _ioctrl_spi2_ss_slew_fast                   _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_SR)
#define _ioctrl_spi2_ss_slew_slow                   _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_SR)
#define _ioctrl_spi2_ss_input_cmos                  _bit_clr(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_IS)
#define _ioctrl_spi2_ss_input_schmitt               _bit_set(IOCTRL->SPI2CR, IOCTRL_SPI2CR_SS_IS)

/*SPI3CR*/
#define _ioctrl_spi3_d_ds_2ma                       _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_DS1_DS0)
#define _ioctrl_spi3_d_ds_4ma                       _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_D_DS1_DS0, IOCTRL_SPI3CR_D_DS1)
#define _ioctrl_spi3_d_ds_8ma                       _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_D_DS1_DS0, IOCTRL_SPI3CR_D_DS0)
#define _ioctrl_spi3_d_ds_12ma                      _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_DS1_DS0)
#define _ioctrl_spi3_d_slew_fast                    _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_SR)
#define _ioctrl_spi3_d_slew_slow                    _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_SR)
#define _ioctrl_spi3_d_input_cmos                   _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_IS)
#define _ioctrl_spi3_d_input_schmitt                _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_D_IS)

#define _ioctrl_spi3_sck_ds_2ma                     _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_DS1_DS0)
#define _ioctrl_spi3_sck_ds_4ma                     _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_SCK_DS1_DS0, IOCTRL_SPI3CR_SCK_DS1)
#define _ioctrl_spi3_sck_ds_8ma                     _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_SCK_DS1_DS0, IOCTRL_SPI3CR_SCK_DS0)
#define _ioctrl_spi3_sck_ds_12ma                    _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_DS1_DS0)
#define _ioctrl_spi3_sck_slew_fast                  _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_SR)
#define _ioctrl_spi3_sck_slew_slow                  _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_SR)
#define _ioctrl_spi3_sck_input_cmos                 _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_IS)
#define _ioctrl_spi3_sck_input_schmitt              _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SCK_IS)

#define _ioctrl_spi3_ss_ds_2ma                      _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_DS1_DS0)
#define _ioctrl_spi3_ss_ds_4ma                      _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_SS_DS1_DS0, IOCTRL_SPI3CR_SS_DS1)
#define _ioctrl_spi3_ss_ds_8ma                      _reg_modify(IOCTRL->SPI3CR, ~IOCTRL_SPI3CR_SS_DS1_DS0, IOCTRL_SPI3CR_SS_DS0)
#define _ioctrl_spi3_ss_ds_12ma                     _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_DS1_DS0)
#define _ioctrl_spi3_ss_slew_fast                   _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_SR)
#define _ioctrl_spi3_ss_slew_slow                   _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_SR)
#define _ioctrl_spi3_ss_input_cmos                  _bit_clr(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_IS)
#define _ioctrl_spi3_ss_input_schmitt               _bit_set(IOCTRL->SPI3CR, IOCTRL_SPI3CR_SS_IS)

/*SWAPCR6*/
#define _ioctrl_swapcr6_swap0_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT0) /**< 0:gint[15] enable; 1:pwm4 enable */
#define _ioctrl_swapcr6_swap0_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT0)
#define _ioctrl_swapcr6_swap1_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT1) /**< 0:ss2 enable; 1:SS_SPI4 enable */
#define _ioctrl_swapcr6_swap1_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT1)
#define _ioctrl_swapcr6_swap2_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT2) /**< 0:sck2 enable; 1:SCK_SPI4 enable */
#define _ioctrl_swapcr6_swap2_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT2)
#define _ioctrl_swapcr6_swap3_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT3) /**< 0:mosi2 enable; 1:SPI4[0] enable */
#define _ioctrl_swapcr6_swap3_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT3)
#define _ioctrl_swapcr6_swap4_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT4) /**< 0:miso2 enable; 1:SPI4[1] enable */
#define _ioctrl_swapcr6_swap4_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT4)
#define _ioctrl_swapcr6_swap5_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT5) /**< 0:txd enable; 1:SPI4[2] enable */
#define _ioctrl_swapcr6_swap5_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT5)
#define _ioctrl_swapcr6_swap6_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT6) /**< 0:rxd enable; 1:SPI4[3] enable */
#define _ioctrl_swapcr6_swap6_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT6)
#define _ioctrl_swapcr6_swap7_clr _bit_clr(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT7) /**< 0:wakeup2 enable; 1:gint0 enable */
#define _ioctrl_swapcr6_swap7_set _bit_set(IOCTRL->SWAPCR6, IOCTRL_SWAPCR6_SWAP_BIT7)

/**
  * @}
  */

/*** 结构体、枚举变量定义 *****************************************************/
#ifdef FILE_OUT
/** @defgroup DRV_IOCTRL_Exported_Types Exported Types
  *
  * @{
  */
#endif

typedef enum
{
	DS_NULL = 0,
	DS_2MA,
	DS_4MA,
	DS_8MA,
	DS_12MA,
} IOCTRL_DSTypeDef;

typedef enum
{
	SR_NULL = 0,
	SR_SLEW_FAST,
	SR_SLEW_SLOW,
} IOCTRL_SRTypeDef;

typedef enum
{
	IS_NULL = 0,
	IS_INPUT_CMOS,
	IS_INPUT_SCHMITT,
} IOCTRL_ISTypeDef;

typedef enum
{
	PS_PULL_NULL = 0,
	PS_PULL_DOWN,
	PS_PULL_UP,
} IOCTRL_PSTypeDef;

typedef enum
{
	IE_INPUT_NULL = 0,
	IE_INPUT_DIS,
	IE_INPUT_EN,
} IOCTRL_IETypeDef;

typedef enum
{
	PUE_PULL_NULL = 0,
	PUE_PULL_DIS,
	PUE_PULL_EN,
} IOCTRL_PUETypeDef;

typedef enum
{
	ODE_OUTPUT_NULL = 0,
	ODE_OUTPUT_CMOS,
	ODE_OUTPUT_OPEN_DRAIN,
} IOCTRL_ODETypeDef;

typedef enum
{
	IOCTRL_SPI1 = 0,
	IOCTRL_SPI2,
	IOCTRL_SPI3,
} IOCTRL_SPIIDTypeDef;

typedef enum
{
	IOCTRL_USI1 = 0,
	IOCTRL_USI2,
} IOCTRL_USIIDTypeDef;

typedef enum
{
	IOCTRL_I2C1 = 0,
	IOCTRL_I2C2,
	IOCTRL_I2C3,
} IOCTRL_I2CIDTypeDef;

typedef enum
{
	IOCTRL_UART1 = 0,
	IOCTRL_UART2,
	IOCTRL_UART3,
} IOCTRL_UARTIDTypeDef;

typedef enum
{
	IOCTRL_SPIM1 = 0,
	IOCTRL_SPIM2,
	IOCTRL_SPIM3,
} IOCTRL_SPIMIDTypeDef;

typedef enum
{
	IOCTRL_GINTL = 0, /* EPORT0 */
	IOCTRL_GINTH,     /* EPORT1 */
	IOCTRL_GINT23_16, /* EPORT2 */
	IOCTRL_GINT31_24, /* EPORT3 */
	IOCTRL_GINT39_32, /* EPORT4 */
	IOCTRL_GINT47_40, /* EPORT5 */
	IOCTRL_GINT55_48, /* EPORT6 */
	IOCTRL_GINT63_56, /* EPORT7 */
} IOCTRL_GINTIDTypeDef;

typedef enum
{
	IOCTRL_SPI_SS = 0x01,
	IOCTRL_SPI_SCK = 0x02,
	IOCTRL_SPI_MISO = 0x04,
	IOCTRL_SPI_MOSI = 0x08,
} IOCTRL_SPIPinTypeDef;

typedef enum
{
	IOCTRL_USI_ISORST = 0x01,
	IOCTRL_USI_ISODAT = 0x02,
	IOCTRL_USI_ISOCLK = 0x04,
} IOCTRL_USIPinTypeDef;

typedef enum
{
	IOCTRL_I2C_SCL = 0x01,
	IOCTRL_I2C_SDA = 0x02,
} IOCTRL_I2CPinTypeDef;

typedef enum
{
	IOCTRL_UART_TXD = 0x01,
	IOCTRL_UART_RXD = 0x02,
	IOCTRL_UART_CTS = 0x08,
} IOCTRL_UARTPinTypeDef;

typedef enum
{
	IOCTRL_PIN_BIT0 = 0x01,
	IOCTRL_PIN_BIT1 = 0x02,
	IOCTRL_PIN_BIT2 = 0x04,
	IOCTRL_PIN_BIT3 = 0x08,
	IOCTRL_PIN_BIT4 = 0x10,
	IOCTRL_PIN_BIT5 = 0x20,
	IOCTRL_PIN_BIT6 = 0x40,
	IOCTRL_PIN_BIT7 = 0x80,
} IOCTRL_PinBitTypeDef;

typedef enum
{
	IOCTRL_SPIM_SS = 0x01,
	IOCTRL_SPIM_SCK = 0x02,
	IOCTRL_SPIM_D0 = 0x04,
	IOCTRL_SPIM_D1 = 0x08,
	IOCTRL_SPIM_D2 = 0x10,
	IOCTRL_SPIM_D3 = 0x20,
} IOCTRL_SPIMPinTypeDef;

typedef enum
{
	TX1_GINT4 = 0x10,
	RX1_GINT0 = 0x01,
	TX2_GINT5 = 0x20,
	RX2_GINT3 = 0x08,
	TX3_GINT1 = 0x02,
	RX3_GINT2 = 0x04,
	TX4_Isoclk2 = 0x01,
	RX4_Isorst2 = 0x02,
	TX5_Isodat2 = 0x04,
	RX5_Isodat1 = 0x08,
	TX6_GINT14 = 0x10,
	RX6_GINT15 = 0x20,
} IOCTRL_UARTSwapGintTypeDef;

typedef enum
{
	SWAP_DIS = 0,
	SWAP_EN,

} IOCTRL_UARTSwapGintENTypeDef;

typedef enum
{
	IOCTRL_SWAP0 = 0,
	IOCTRL_SWAP1,
	IOCTRL_SWAP2,
	IOCTRL_SWAP3,
	IOCTRL_SWAP4,
	IOCTRL_SWAP5,
	IOCTRL_SWAP6,
	IOCTRL_SWAP7,
	IOCTRL_SWAP8,
	IOCTRL_SWAP9,
	IOCTRL_SWAP10,
	IOCTRL_SWAP11,
	IOCTRL_SWAP12,
	IOCTRL_SWAP13,
	IOCTRL_SWAP14,
	IOCTRL_SWAP15,
	IOCTRL_SWAP16,
	IOCTRL_SWAP17,
	IOCTRL_SWAP18,
	IOCTRL_SWAP19,
	IOCTRL_SWAP20,
	IOCTRL_SWAP21,
	IOCTRL_SWAP22,
	IOCTRL_SWAP23,
	IOCTRL_SWAP24,
	IOCTRL_SWAP25,
	IOCTRL_SWAP26,
	IOCTRL_SWAP27,
	IOCTRL_SWAP28,
	IOCTRL_SWAP29,
	IOCTRL_SWAP30,
	IOCTRL_SWAP31,
} IOCTRL_SwapTypeDef;

typedef enum
{
	IOCTRL_PSRAM1 = 0,
	IOCTRL_PSRAM2,
	IOCTRL_PSRAM3,
} IOCTRL_PSRAMIDTypeDef;

typedef enum
{
	IOCTRL_EPORT0 = 0,
	IOCTRL_EPORT1,
	IOCTRL_EPORT2,
	IOCTRL_EPORT3,
	IOCTRL_EPORT4,
	IOCTRL_EPORT5,
	IOCTRL_EPORT6,
	IOCTRL_EPORT7,
} IOCTRL_EPORTIDTypeDef;

typedef enum
{
	PIN_INPUT = 0,
	PIN_OUTPUT,
} IOCTRL_PinDirTypeDef;

typedef enum
{
	IOCTRL_PWMT_ETR = 0x00,
	IOCTRL_PWMT_BRK,
} IOCTRL_PWMTPinTypeDef;

/**
  * @}
  */

/*** 全局变量声明 **************************************************************/
#ifdef FILE_OUT
/** @defgroup DRV_IOCTRL_Exported_Variables Exported Variables
  *
  * @{
  */
#endif

/**
  * @}
  */

/*** 函数声明 ******************************************************************/
#ifdef FILE_OUT
/** @defgroup DRV_IOCTRL_Exported_Functions Exported Functions
  * @{
  */
#endif

extern void DRV_IOCTRL_SetSPI1DS(uint8_t pins, IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetSPI2DS(uint8_t pins, IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetSPI3DS(uint8_t pins, IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetSPI1SR(uint8_t pins, IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetSPI2SR(uint8_t pins, IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetSPI3SR(uint8_t pins, IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetSPI1IS(uint8_t pins, IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetSPI2IS(uint8_t pins, IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetSPI3IS(uint8_t pins, IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetSPI1PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetSPI2PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetSPI3PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetSPI1IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetSPI2IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetSPI3IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetUSIDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetUSISR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetUSIIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetUSI1PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetUSI1DIEN(uint8_t pins, FunctionalState status);
extern void DRV_IOCTRL_SetUSI2DREN(FunctionalState status);
extern void DRV_IOCTRL_SetUSI2PUEN(uint8_t pins, FunctionalState status);
extern void DRV_IOCTRL_SetUSI2DIEN(uint8_t pins, FunctionalState status);
extern void DRV_IOCTRL_SetI2CDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetI2CSR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetI2CIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetI2C1PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetI2C2PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetI2C3PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetI2C1IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetI2C2IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetI2C3IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetUARTDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetUARTSR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetUARTIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetUART1PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetUART2PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetUART3PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetUART1CTSPUE(IOCTRL_PUETypeDef pue);
extern void DRV_IOCTRL_SetUART2CTSPUE(IOCTRL_PUETypeDef pue);
extern void DRV_IOCTRL_SetUART3CTSPUE(IOCTRL_PUETypeDef pue);
extern void DRV_IOCTRL_UARTSwapGint(uint8_t pins, IOCTRL_UARTSwapGintENTypeDef swap);
extern void DRV_IOCTRL_UARTSwapIso(uint8_t pins, IOCTRL_UARTSwapGintENTypeDef swap);
extern void DRV_IOCTRL_SetGINTLDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetGINTLSR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetGINTLIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetGINTLIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetGINTLPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetGINTHDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetGINTHSR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetGINTHIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetGINTHIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetGINTHPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetSPIM1DS(uint8_t pins, IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetSPIM1SR(uint8_t pins, IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetSPIM1IS(uint8_t pins, IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_SetSPIM1PUE(IOCTRL_PUETypeDef pue);
extern void DRV_IOCTRL_SetSPIM1ODE(IOCTRL_ODETypeDef ode);
extern void DRV_IOCTRL_SetSPIM1IE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetSPIM1PS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SwapEnable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_SwapDisable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap2Enable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap2Disable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap3Enable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap3Disable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap4Enable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap4Disable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap5Enable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap5Disable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap6Enable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_Swap6Disable(IOCTRL_SwapTypeDef pSwap);
extern void DRV_IOCTRL_SetWKUPPADCRDS(IOCTRL_DSTypeDef ds);
extern void DRV_IOCTRL_SetWKUPPADCRSR(IOCTRL_SRTypeDef sr);
extern void DRV_IOCTRL_SetWKUPPADCRIS(IOCTRL_ISTypeDef is);
extern void DRV_IOCTRL_PSRAMCREnableDisable(IOCTRL_PSRAMIDTypeDef id, FunctionalStateTypeDef en);
extern void DRV_IOCTRL_EPORT2PinDirection(IOCTRL_PinBitTypeDef pin, IOCTRL_PinDirTypeDef dir);
extern void DRV_IOCTRL_EPORT5PinDirection(IOCTRL_PinBitTypeDef pin, IOCTRL_PinDirTypeDef dir);
extern void DRV_IOCTRL_EPORT6PinDirection(IOCTRL_PinBitTypeDef pin, IOCTRL_PinDirTypeDef dir);
extern void DRV_IOCTRL_EPORT7PinDirection(IOCTRL_PinBitTypeDef pin, IOCTRL_PinDirTypeDef dir);
extern void DRV_IOCTRL_SetEPORT2CRPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetEPORT2CRIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetEPORT5CRPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetEPORT5CRIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetEPORT6CRPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetEPORT6CRIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SetEPORT7CRPS(uint8_t pins, IOCTRL_PSTypeDef ps);
extern void DRV_IOCTRL_SetEPORT7CRIE(uint8_t pins, IOCTRL_IETypeDef ie);
extern void DRV_IOCTRL_SwdOpen(void);
	/**
* @}
*/

	/**
*@}
*/

	/**
*@}
*/

#ifdef __cplusplus
}
#endif

#endif /* __IOCTRL_DRV_H */

/************************ (C) COPYRIGHT C*Core *****END OF FILE*************/
